Field of the Disclosure
This disclosure relates generally to current mode logic (CML) clock circuits, more specifically, to controlling phase of CML clock circuits.
Description of Related Art
This description of related art is provided for the purpose of generally presenting a context for the disclosure that follows. Unless indicated otherwise herein, concepts described in this section are not prior art to this disclosure and are not admitted to be prior art by inclusion herein.
Many electronic devices include a modem that enables communication of data via a wireless network. As users and applications of devices consume increasing amounts of data through the wireless networks, network providers and equipment manufacturers have implemented advanced communication techniques to increase spectrum efficiency. Many of these advanced techniques implement multiple-input multiple-output (MIMO) and carrier aggregation (CA), which increase wireless data capacity by using multiple spatial streams of communication.
To facilitate communication over multiple spatial streams, wireless transceivers include multiple transmit and receive chains to process data carried by each of the spatial streams. As with conventional transceivers, modulation and frequency conversion operations are performed using reference clock signals provided by a local oscillator (LO) and frequency dividers. With multiple transmit and receive chains, however, MIMO- and CA-capable transceivers often have a respective LO and frequency divider associated with each chain. Because an initial state of a frequency divider is unknown at start up, starting up multiple LOs and frequency dividers may result in out-of-phase LO signals. These out-of-phase LO signals often cause bi-modal direct current (DC) offset, which prevents some transmission operations, such as beam forming, or degrades receiver sensitivity.